The escalating requirements for high density and performance associated with ultra-large scale integration technology creates significant challenges for the design and implementation of electrical connections between circuit components and external electrical circuitry. Integrated circuit (IC) devices, whether individual active devices, individual passive devices, multiple active devices within a single chip, or multiple passive and active devices within a single chip, require suitable input/output (I/O) connections between themselves and other circuit elements or structures.
Device miniaturization and the ever increasing density of semiconductor devices require an ever increasing number of I/O terminals as well as improvements in the electrical connections. One technique that supports the increased device densities involves a shift from peripheral wire bonding to area array chip interconnects. An example of an area array interconnect packaging technology is the flip chip technology. In the flip chip technology, a large area array of solder bumps on the surface of the die directly couple the “flipped” die to respective solder pads on the surface of the package substrate. In one implementation, a large number of pin leads are soldered to respective solder fillets on the opposite surface of the package substrate, resulting in a pin grid array package. The pin grid array package accommodates an increased number of I/O terminals and provides electrical signals immediately below the chip.
Presently, lead (Pb) is used as a primary constituent of solder and, for example, up to 95 wt % of solder can be lead (Pb). Thus, the use of solder in solder bumps, solder pads on the die side of the package substrate, and solder fillets on the pin side of the package substrate, translates into a pervasive and extensive use of lead (Pb). However, an alternative to lead (Pb) is highly desirable since, for example, environmental regulations call for elimination of lead (Pb) in electronic circuits. This requirement creates significant challenges for replacing lead (Pb) in the solder materials. As shown in the example of a pin grid array discussed above, solder containing lead (Pb) is the most widely used interconnect material in semiconductor packaging technology.
However, replacing the long-established use of lead (Pb) in solder with other materials represents significant challenges. For example, the processing “temperature hierarchy” must be maintained, while reliable electrical contacts and mechanical connections need be made. As an example, in flip chip technology the processing temperature hierarchy dictates use of solder fillets for pin solder that have a reflow temperature, i.e. the temperature at which the solder is mobile enough to form an electrical connection, below an organic substrate decomposition temperature. Furthermore, solder used is solder pads on the die side of the package substrate should have a reflow temperature below the solder in the solder fillets used in pin solder.
Thus, there is need in the art for replacing the long-entrenched use of lead (Pb) in solder with other materials, while maintaining reliable electrical contacts and the required mechanical strength, and while also complying with the required processing temperature hierarchy in assembling a semiconductor package, such as assembling a flip chip in a pin grid array package with an organic substrate.